Leaderboard
The best QEC design under 200 ions
Lowest logical error rate per round per logical qubit, any curated code.
The Goal 1 leaderboard →A verified resource estimate for Shor's algorithm
Ions, time and machine, with every step compiled and checked.
Shor's algorithm for 15 →One code at a time, every architecture
For each fixed code, the fastest and the most reliable machine in each architecture family.
The Goal 3 figures →Loading Goal 1…
FTL’s target: 60 logical qubits within 2000 ions, about 33 ions per logical qubit. The Goal 1 chart: every entry, rank by any measure →
Architecture
Machines, compiled by the reference compiler and judged by every rule. The three fastest verified designs per board; memory boards rank by logical error rate, and the C2LR boards rank swap-or-stay lattices apart.
BB [[144,12,12]], Bravyi's schedule
One syndrome round of the bivariate-bicycle [[144,12,12]] code in Bravyi et al.'s schedule (Fig. 5 of arXiv:2308.07915): one ancilla per check, so 144 data ions and 144 check ions, and 864 two-qubit gates in the schedule's order, which every programme on the board keeps.
QEC clock: 288 ms a round · 3 cycles/s · decoder margin 288,370× with a lookup table (fpga) · feedback 0.0029% of a cycle what this means →
Loading the official ranking…
Repetition code, distance 9
One syndrome-extraction round of the distance-9 repetition code: 8 weight-2 Z checks.
QEC clock: 2.91 ms a round · 344 cycles/s · decoder margin 2,910× with a lookup table (fpga) · feedback 0.29% of a cycle what this means →
Loading the official ranking…
Five-qubit code [[5,1,3]]
One syndrome-extraction round of the [[5,1,3]] code: four weight-4 mixed-Pauli checks.
QEC clock: 9.15 ms a round · 109 cycles/s · decoder margin 9,155× with a lookup table (fpga) · feedback 0.091% of a cycle what this means →
Loading the official ranking…
Steane code [[7,1,3]]
One syndrome-extraction round of the Steane code: three X and three Z weight-4 checks.
QEC clock: 9.79 ms a round · 102 cycles/s · decoder margin 9,785× with a lookup table (fpga) · feedback 0.085% of a cycle what this means →
Loading the official ranking…
Surface code, distance 3 (17 qubits)
One syndrome-extraction round of the distance-3 rotated surface code: eight stabilizers on 9 data qubits.
QEC clock: 11.7 ms a round · 86 cycles/s · decoder margin 11,665× with a lookup table (fpga) · feedback 0.071% of a cycle what this means →
Loading the official ranking…
Memory boards: the logical error rate
Repetition code memory, distance 5
The study’s designs, with 95% intervals (statistically tied at this budget)
1h2_racetrack0 errors in 200,000 shots (below 3.8e-06)2cyclone_dual_loop_j0 errors in 200,000 shots (below 3.8e-06)3cyclone_base_j0 errors in 200,000 shots (below 3.8e-06)Loading the official ranking…
Surface code memory, distance 3
The study’s designs, with 95% intervals
1ring24_8_j4.00e-04 (3.5e-04 to 4.6e-04)2cyclone_base_j4.49e-04 (3.9e-04 to 5.2e-04)3ladder_2x724.54e-04 (4.0e-04 to 5.2e-04)Loading the official ranking…
C2LR boards: swap-or-stay lattices
The memory boards’ own experiments on C2LR lattices (arXiv:2403.00756), where crystals move only by swap-or-stay steps: one shared junction waveform, one direction bit per leg. Ranked here, board by board, and not against the shuttle boards; the reference entries are the baseline C2LR router’s.
Repetition code memory, distance 5, on C2LR (Ba-Sr)
The study’s designs, with 95% intervals (statistically tied at this budget)
1c2lr5x20 errors in 200,000 shots (below 3.8e-06)2c2lr3x30 errors in 200,000 shots (below 3.8e-06)3c2lr4x41.00e-06 (1.8e-07 to 5.7e-06)Loading the official ranking…
Repetition code memory, distance 5, on C2LR (Yb-Ba)
The study’s designs, with 95% intervals (statistically tied at this budget)
1c2lr5x20 errors in 200,000 shots (below 3.8e-06)2c2lr4x40 errors in 200,000 shots (below 3.8e-06)3c2lr5x50 errors in 200,000 shots (below 3.8e-06)Loading the official ranking…
Surface code memory, distance 3, on C2LR (Ba-Sr)
The study’s designs, with 95% intervals
1c2lr4x44.93e-04 (4.3e-04 to 5.6e-04)2c2lr4x55.46e-04 (4.8e-04 to 6.2e-04)3c2lr5x55.46e-04 (4.8e-04 to 6.2e-04)Loading the official ranking…
Surface code memory, distance 3, on C2LR (Yb-Ba)
The study’s designs, with 95% intervals
1c2lr4x45.67e-04 (4.9e-04 to 6.5e-04)2c2lr4x55.92e-04 (5.2e-04 to 6.8e-04)3c2lr5x55.92e-04 (5.2e-04 to 6.8e-04)Loading the official ranking…
The QEC clock cycle
A round is half a cycle: the decoder closes the loop. Drawn for the slowest board (BB [[144,12,12]], Bravyi's schedule), tabulated for all.
syndrome extraction 288 ms · outcomes to the decoder 5 µs · decode 1 µs · frame update 100 ns · resolve the guard 200 ns · decision to the place 2 µs
| board | a round | cycles/s | Lookup table (FPGA) margin | Belief propagation on an FPGA margin | Belief propagation on a GPU margin | reaction | of a cycle |
|---|---|---|---|---|---|---|---|
| BB [[144,12,12]], Bravyi's schedule | 288 ms | 3 | 288,370× | 600,771× | 288× | 8.3 µs | 0.0029% |
| Repetition code, distance 9 | 2.91 ms | 344 | 2,910× | 6,062× | 2.9× | 8.3 µs | 0.29% |
| Five-qubit code [[5,1,3]] | 9.15 ms | 109 | 9,155× | 19,073× | 9.2× | 8.3 µs | 0.091% |
| Steane code [[7,1,3]] | 9.79 ms | 102 | 9,785× | 20,385× | 9.8× | 8.3 µs | 0.085% |
| Surface code, distance 3 (17 qubits) | 11.7 ms | 86 | 11,665× | 24,302× | 12× | 8.3 µs | 0.071% |
| for scale: superconducting (Google's surface-code experiments (arXiv:2207.06431, 2408.13687)) | 1 µs | 1,000,000 | 1× | 2.1× | 0.001× | 8.3 µs | 830% |
What margin and reaction mean
Margin is the round time divided by the decoding time: above 1× the decoder keeps up and the undecoded backlog never grows; below it, the backlog grows every round and no amount of buffering fixes it. That is why the trapped-ion rows are comfortable with a decoder that the superconducting row cannot afford — the ion transport that makes a QCCD round slow also makes its classical loop nearly free.
Reaction is the last measurement to a usable decision: 5 µs on the wire to the control system (AQT M-ACTION, arXiv:2101.11390), the decode, 100 ns to write the frame, and for a guarded operation 2.2 µs to resolve it and reach the place. It is what a non-Clifford gate waits for, and it is checked in the schedule (G10, G11) of every algorithm under Logical Algorithm.
the decoder's answer stops in the classical memory as a Pauli-frame update; no ion waits for it, so the cycle is the quantum round and the classical side only has to keep up — and, in the other mode, something waits for the answer -- a conditional operation, a branch, the S̄ correction of a T teleportation -- so the cycle also carries the reaction time, and the decision has to reach the place before its op may start
Official submissions: more boards
The other boards the official server ranks, live.
Loading the official leaderboard...
How to take part
Press Try your own design on a
board: your own QCCD workspace opens on it, you test a design with the same checks, and press
Submit (signed in with your qccd.academy account, which the leaderboard credits). In a
terminal: qccd login, qccd submit --local --board "BB [[144,12,12]]" --wait,
then qccd publish --submission <id>.
Compiler
Submit a compiler: it runs on 108 circuit–machine pairs, plus 8 hidden ones, ranked by speedup over the reference.
Compiler benchmark suite@1
The suite, pair by pair, and how to submit →
The measures
| metric | what it measures | |
|---|---|---|
speedup | high is better | geometric mean over pairs both compilers compiled validly of T_jones(reference) / T_jones(yours) |
coverage | high is better | pairs compiled validly / pairs in the suite |
ler_ratio | low is better | geometric mean over memory pairs both compiled of LER(yours) / LER(reference) |
wrong | low is better | pairs where the program failed a rule or does not implement the circuit (any makes the entry ineligible) |
compile_seconds | low is better | total wall time of the compiler over the suite (reported, not ranked) |
Official ranking
Loading the official ranking...